Nuvia and the development of Oryon
The Nuvia startup emerged from stealth mode in 2019 with a specific mission. The leadership team included several prominent chip architects, including one former Apple engineer. This team aimed to design a power efficient core capable of surpassing the designs from AMD, Apple, Arm, and Intel. Qualcomm acquired Nuvia in 2021 to integrate this staff into its internal CPU development efforts. This acquisition revitalized Qualcomm’s CPU projects, leading to the Oryon core found in the Snapdragon X Elite. For those who followed Nuvia since its inception, the arrival of this architecture follows a long wait of nearly five years.
The Oryon architecture represents a shift for Qualcomm, which last released a smartphone SoC with internally designed cores almost eight years ago. While many companies choose to purchase off-the-shelf core IP from Arm, Qualcomm developed Oryon to compete directly with mainstream x86 processors. The design is an ARMv8.7 architecture, which uses a slightly older instruction set architecture level than the current ARMv9 licensable Cortex cores. This means Oryon relies on the Neon SIMD extension rather than the SVE or SVE2 instructions. This choice maintains compatibility with existing software, though it remains to be seen if Microsoft will eventually mandate ARMv9 for Windows.
Cluster configuration and latency
The Snapdragon X Elite implements 12 Oryon cores in three quad-core clusters. Each cluster holds 12 MB of L2 cache with 12-way associativity. This L2 cache handles requests from all four cores in the cluster. It has an average latency of 17 cycles. The L2 TLB has 8-way associativity and more than 8,000 entries. This cache is inclusive, so the L1 cache contents of all cores in a cluster stay copied in it. This design simplifies coherency handling and improves power efficiency.
The clustered arrangement creates distinct performance characteristics during core to core latency tests. Transfers within a single cluster move quickly, but cross-cluster transfers incur high latency. This differs from the 8cx Gen 3, which used four Cortex X1 cores and four Cortex A78 cores with an Arm DSU interconnect and shared L3. Apple also uses quad-core clusters with a shared L2, but the M1 uses a hybrid core arrangement. The Snapdragon X Elite avoids a hybrid configuration, opting instead to run its clusters at different maximum clocks to balance single threaded and multithreaded performance.
The memory subsystem also relies on a System Level Cache to manage data. This SLC can service multiple blocks on the chip, but it provides lower performance than a cache dedicated to a single block. The SLC has a capacity of 6 MB and achieves a latency of 26 to 29 ns. It also provides a bandwidth of 135 GB/s in both directions. This bandwidth matches the requirements for DRAM. You already know that efficient data movement is necessary to prevent execution stalls in high-performance cores.
Power management and thermal behavior
Power management policies vary significantly across the competitive landscape. On battery power, the Snapdragon X Elite does not reach maximum clock speeds until more than 110 ms after a load is applied. This delay helps extend battery life by avoiding high power states during short bursts of activity. Intel Meteor Lake takes this approach further and does not reach maximum boost clocks on battery at all. AMD maintains a faster boost policy, reaching 5 GHz in a millisecond or less on both wall and battery power.
Thermal behavior changes when the processor runs on wall power. In a Samsung Galaxy Book4 Edge, the CPU does not idle, which improves responsiveness. The cores start at 3.4 GHz and can reach 4 GHz in 1.44 milliseconds. However, this policy makes the laptop warmer even when it is idle. This warmth is not a trait shared by Meteor Lake or the AMD Phoenix architecture.
The Snapdragon X Elite is a 4 nm SoC. It uses a dual core boost feature to optimize demanding workloads. The single core performance competes with high end x86 chips, while its power efficiency aims to provide multiple days of battery life. The Snapdragon X Elite can run generative AI models with over 13 billion parameters on the device. This capability depends on the coordination between the CPU, the Adreno GPU, and the Hexagon NPU.
Frontend decoding and instruction width
The frontend of the Oryon core manages the translation of instructions into micro-ops. Oryon uses 8 parallel decoders to handle the instruction stream. The L1 instruction cache has a capacity of 192 KB with 6-way associativity. It can fetch up to 16 instructions, or 64 bytes, each cycle. This L1i cache includes a first-level iTLB with 256 entries and 8-way associativity.
The L1 data cache has a capacity of 96 KB and also uses 6-way associativity. This cache provides a load-to-use latency of 4 cycles. This latency is comparable to the Apple Firestorm core, though Firestorm had a 3 cycle latency at a lower clock speed. The data L1 TLB has 224 entries and 7-way associativity. The reorder buffer (RoB) allows the core to see a window of more than 650 operations. This capacity is larger than the 576 operations found in the Intel Lion Cove core.
The core uses over 400 physical general registers and over 400 physical SIMD/FPU registers for renaming architectural registers. Oryon has move elimination, though it is not as robust as the implementations from Intel or AMD for chained dependent MOVs. It does not use zeroing idiom recognition for XOR-ing a register with itself. Moving an immediate value of zero to a register works to break dependencies.
Branch prediction and control flow
Branch prediction determines how much energy a CPU spends on wasted work. Oryon has a misprediction penalty of 13 cycles, which matches the common case for AMD Zen 4. The direction predictor tells the branch predictor the likely direction, and Oryon uses a single level direction predictor similar to the architecture found in Intel Golden Cove. The branch target buffer (BTB) caches branch destination addresses to speed up the process.
The branch target buffer ties to the instruction cache, which means that taken branches see higher latency as the test loop spills out of the 192 KB L1 instruction cache. Within an 8 KB footprint, branches can be handled with single cycle latency. If the branch footprint is larger, the core can do one taken branch every three cycles as long as the code fits in the 192 KB L1i. This is similar to how Apple’s M1 handles branching, though M1 achieves single cycle branching within a 4 KB footprint.
The indirect branch predictor in Oryon has 2048 entries. This is smaller than the 3072 entry indirect predictor in Zen 4. However, Oryon does not suffer from a slowly increasing penalty after 32 targets for a single branch. The return stack in Oryon has 48 entries. This is deeper than the 32 entry return stack in Zen 4. When the return stack capacity is exceeded, the core clears the stack, which causes a sharp increase in call and return time.
Execution pipelines and throughput
The integer portion of the Oryon core uses 6 pipelines and 6 ALUs. Four of these ALUs are simple, while two are complex. This configuration allows the core to perform two multiplications per cycle. Each of the six pipelines has a 20-entry Reservation Queue in front of it. The integer scheduler has 120 entries, which is larger than the 96 entries in Zen 4 and the 97 entries in Intel Golden Cove.
The vector side of the core uses 4 pipes. The vector scheduler is very large with 192 combined entries. This exceeds the 128 entries in Zen 4 and the 75 entries in the Cortex X2. The instruction throughput for vector operations in Oryon is nearly identical to the Apple Firestorm core. However, Oryon has a 2 cycle latency for SIMD INT MUL, whereas Firestorm has a 3 cycle latency. Like Firestorm and the M3 P-Core, Oryon lacks SVE or SVE2 instructions and uses Neon for SIMD operations.
The Load/Store Unit (LSU) has 4 ports. The store pipes share ports with the load pipes. Specifically, the LSU has four ports, p6 through p9, which handle load operations. The p10 and p11 ports handle standard operations that must work with the load pipes. Oryon can perform 4 loads per cycle, regardless of whether the loads are scalar or vector. This load bandwidth is higher than other CPUs in this lineup. The memory scheduler can fill 64 entries with store instructions.
Memory hierarchy and the HBM4 squeeze
The memory subsystem for the Snapdragon X Elite uses LPDDR5X at an effective speed of 8448 MHz. It uses eight 16-bit channels, creating a 128-bit memory width. This width is the same as the basic Apple M1 through M4 processors. The maximum amount of RAM available for these PCs is 64 GB. RAM latency is typically between 102 and 104 ns.
The current market for memory is influenced by the demand for High Bandwidth Memory (HBM4). Because HBM4 requires roughly three times the wafer capacity of conventional DRAM for the same output, manufacturers have shifted fabrication capacity away from consumer parts toward high-margin AI infrastructure products. This shift has increased the cost of consumer memory. In the second quarter of 2026, consumer memory prices rose by as much as 89 percent.
For users looking to manage AI workloads, the amount of RAM is a determining factor. A 32 GB configuration is the target for machines intended to run local AI features or heavy multitasking. 16 GB remains a sufficient configuration for standard business tasks like web browsing and office suites.
| Spec Component | Value/Detail |
|---|---|
| L2 Cache Capacity | 12 MB per cluster |
| L2 Cache Associativity | 12-way |
| L1 Instruction Cache | 192 KB |
| L1 Data Cache | 96 KB |
| Reorder Buffer | > 650 operations |
| Branch Mispredict Penalty | 13 cycles |
| Return Stack | 48 entries |
| Integer ALUs | 6 |
| Vector Pipes | 4 |
| Memory Bandwidth | 135 GB/s |
| Max RAM Capacity | 64 GB |
Comparison with existing architectures
The Oryon architecture competes with established x86 and ARM designs. AMD’s Phoenix SoC uses eight Zen 4 cores in a single cluster with 16 MB of L3 cache. Because all cores are in one cluster, AMD shows very low core to core latency. Intel Meteor Lake uses a hybrid setup with six Redwood Cove performance cores and eight Crestmont efficiency cores. The performance cores and regular efficiency cores in Meteor Lake share a 24 MB L3 cache.
Oryon’s single-threaded performance competes with the Apple M2 Max. In some tests, the Snapdragon X Elite outperforms the M2 Max in single threaded performance while matching its peak performance at 30% less power. The Snapdragon X Elite also beats the Intel i9-13980Hx in single threaded performance, matching its peak performance at 70% less power.
The core design presents a trade-off between extreme clock speeds and cluster efficiency. While Zen 4 maintains a clock speed advantage, the gap is smaller in mobile applications. Oryon provides a high reordering capacity and wide execution, but its cross-cluster latency remains higher than the single-cluster designs from AMD. One question remains about how Qualcomm will manage the transition to the ARMv9 instruction set as Microsoft updates Windows requirements.
